The present invention relates to an arrangement for using a serial-PCI connection between computing devices and remote mass data storage-devices in order to create highly accessible, flexible, high-performance, low-cost storage systems.
U.S. Pat. No. 6,421,760 teaches a high performance RAID system for a PC that includes a controller card that controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a micro-controller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the micro-controller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes). The packets also carry transfer commands and target addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the micro-controller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol that guarantees a minimum I/O bandwidth to each disk drive. This minimum I/O bandwidth is preferably greater than the sustained transfer rate of each disk drive, so that all drives of the array can operate at the sustained transfer rate without the formation of a bottleneck.
U.S. Pat. No. 6,388,590 teaches a transmission interface that is compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals is single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals is also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus. The third set of signals is serial to one another, and use low voltage level, differential signaling. The third set of signals is suited for transmission by the serial bus, which includes many fewer wires than available in an IDE bus while operating at a faster data rate.
U.S. Pat. No. 6,363,211 teaches video data and audio data inputted respectively from a camera system and a microphone that are compressed and encoded in a video compressor/expander-encoder/decoder and an audio compressor/expander-encoder/decoder respectively, and then are multiplexed in a multiplexer. Subsequently the multiplexed data are supplied to a hard disk drive via an AV interface, a host bus, an interface adaptor and an interface. Information representing the kind of the data is written in a register. The data supplied to the hard disk drive are recorded in a disk, on the basis of such information, by a method conforming to the data. And in a reproduction mode, the data are reproduced, on the basis of such information, by a method conforming to the data. Thus, the data can be recorded or reproduced efficiently by the relevant method conforming to the kind of the data.
U.S. Pat. No. 6,188,571 teaches a method and apparatus for a mass storage subsystem such as a RAID array that includes a housing which defines first and second cavities with the first cavity housing an array controller such as a RAID controller. The second cavity houses a plurality of substantially conventional IDE drives conforming to the 3.5″ form factor. The array is configured to maximize cooling of the array controller and the drives within the extremely small space defined by the housing.
U.S. Pat. No. 6,134,630 teaches a high-performance RAID system for a PC that includes a controller card that controls an array of ATA disk drives. The controller card includes an array of automated disk drive controllers, each of which controls one respective disk drive. The disk drive controllers are connected to a micro-controller by a control bus and are connected to an automated coprocessor by a packet-switched bus. The coprocessor accesses system memory and a local buffer. In operation, the disk drive controllers respond to controller commands from the micro-controller by accessing their respective disk drives, and by sending packets to the coprocessor over the packet-switched bus. The packets carry I/O data (in both directions, with the coprocessor filling-in packet payloads on I/O writes), and carry transfer-commands and target-addresses that are used by the coprocessor to access the buffer and system memory. The packets also carry special completion values (generated by the micro-controller) and I/O request identifiers that are processed by a logic circuit of the coprocessor to detect the completion of processing of each I/O request. The coprocessor grants the packet-switched bus to the disk drive controllers using a round robin arbitration protocol that guarantees a minimum I/O bandwidth to each disk drive. This minimum I/O bandwidth is preferably greater than the sustained transfer rate of each disk drive, so that all drives of the array can operate at the sustained transfer rate without the formation of a bottleneck.
U.S. Pat. No. 6,003,105 teaches a long-haul PCI bridge pier that includes a PCI interface for connection to a PCI bus and a high speed link interface for connection to a high speed link. A PCI adapter is operative to transform PCI information received at the PCI interface into high-speed information to be transmitted through the high speed interface and is operative to transform high speed information received at the high speed interface into PCI information to be transmitted through the PCI interface. The PCI bridge pier permits remote-connection of a PCI bus with a high-speed link such as a serial link. Two such PCI bridge piers, in combination with a high-speed link may be used for implementing a long haul PCI-to-PCI-bridge.
U.S. Pat. No. 5,967,796 teaches an interface cable that allows access to an operational Peripheral Component Interconnect (PCI) bus compatible circuit board is disclosed. A flat flexible cable secures a plurality of connectors at substantially equal intervals. The connectors on the flat cable are adapted to receive a connection on a first edge of the PCI compatible circuit board. When the PCI compatible circuit board is plugged into the flat flexible cable, a second edge of the PCI compatible circuit board which is opposite the first edge is free to move laterally, away from neighboring circuit boards in response to a flexing of the flat flexible cable. Open space is created adjacent to the PCI compatible circuit board allowing sufficient access to surfaces of the functioning PCI compatible circuit board for testing purpose.
U.S. Pat. No. 5,948,092 teaches a personal computer system that includes a first housing coupled to a second housing with a multi-conductor cable. The first housing includes an IDE direct access storage device having an opening for receiving a removable storage medium. The second housing is separate from the first housing and includes a microprocessor coupled to a local bus and an expansion bus, a first IDE controller, a non-volatile storage device coupled to the local bus and a power supply. The cable is coupled to the first and second housings for electrically connecting devices in the first housing to devices in the second housing. The second housing has a first interface coupled to the expansion bus, the first IDE controller and the cable. The first housing includes a second interface coupled to the cable and the IDE device. The first interface is operative to determine when a bus cycle initiated by a device in the second housing is directed to the IDE device in the first housing and to transfer data from the IDE controller to the IDE device via the cable and the second interface when a bus cycle is directed to the IDE device.
U.S. Pat. No. 5,905,885 teaches a peripheral interface system that includes a pair of integrated circuits, referred to as a system adapter and a socket controller, that use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system-adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol that may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.
U.S. Pat. No. 5,987,533 teaches a SCSI bus-based mass storage system for automatically setting the addresses of a plurality of disk devices that includes a SCSI controller for providing predetermined SCSI address signals including addresses data for each peripheral device, and a SCSI ID input device which receives and stores and forwards the corresponding SCSI address ID to the peripheral devices for setting the SCSI ID of addressable peripheral devices. The SCSI controller includes an N-bit shift register having a serial output for providing the SCSI address signals, and a counter for providing the clock signals. Further, the SCSI ID input device includes a plurality of M-bit shift registers which correspond to the number of addressable peripheral devices, where M corresponds to the number of SCSI ID setting jumpers provided in the peripheral devices. Since a manual jumper setting for the SCSI ID can be avoided, faster and more convenient use of the SCSI devices is possible when one or more SCSI devices are added to the computer system. Disk drives and controllers for personal computers have been developed that utilize the SCSI bus standard for control and transfer of data to be stored. SCSI bus-based mass storage systems typically use a large number of disk drives to achieve the required data capacities. As is well known, the SCSI serial interface takes roles of a connection path that transfers commands issued by the computer to many peripheral devices. The controller performs controlling of the peripheral device and is embedded in the same peripheral device. Therefore, the SCSI interface acts like a “network card” and provides features of error detection and restoration, detecting and controlling of data collision, and communication with the other devices. Also, there are benefits to distributing data across a large number of smaller capacity drives including faster average access time, higher data transfer rate, improved mass storage system reliability, and reduced data loss in the event of a drive failure. In an earlier SCSI bus-based mass storage system, a SCSI bus interconnects a SCSI controller with peripheral devices. The SCSI controller includes a host adaptor that is in communication with a computer, and the peripheral devices commonly include their own controllers. In this storage system, the peripheral devices are usually hard disk drives, and may include CD-ROM drives. According to the SCSI-I standard, only eight device addresses are possible in that there is one host controller and seven peripheral devices. If more than seven peripheral devices are required, multiple host controllers must be added to the mass storage system. Meanwhile, those peripheral devices (hereinafter “SCSI devices” or “devices”) report their SCSI address ID to the computer system via the SCSI bus in the computer booting process. The SCSI devices commonly include jumper-setting blocks. Therefore, in the event of adding an SCSI device in the computer system, it is difficult for users to set the SCSI address ID by hand, and the jumper setting procedure required at every addition of the SCSI device is annoying and time-consuming. To overcome the limitation of the number of SCSI devices, the SCSI-II standard has been established which allows the device addressing to be increased to a limit of sixteen devices. Further, a method for sharing device addresses between different devices on the SCSI bus to thereby increase the number of devices that can utilize the bus has been disclosed in U.S. Pat. No. 5,367,647. The sharing is SCSI address ID number between the SCSI host adaptor and a SCSI device controller on the bus. While the number of addressable SCSI devices is remarkably increased, the manual jumper setting for the SCSI address ID and serviceability problems remain.
U.S. Pat. No. 5,822,184 teaches a modular data device assembly for a computer is disclosed that has a housing that is designed to fit into a conventional, industry standard size expansion bay. Individual plug-in data storage devices such as hard disk drives or CD-ROM drives are disposed vertically in a stacked formation within the housing. A motherboard with plug-in connectors to which the drives are connected allows easy replacement of defective data devices, which devices slide in or out. The disk drives and modular data device assemblies may be arrayed in series or in parallel to a controller. By its modular structure and redundant storage functions the modular data device assembly benefits from what is known as Redundant Array of Independent Disks principle.
U.S. Pat. No. 5,224,019 teaches a modular computer chassis that includes a main chassis to which a motherboard is attached and a sub-chassis attachable to the main chassis. The sub-chassis holds at least one computer component and is electrically connected to the motherboard. In this manner, the computer component is separable from the main chassis by removing the sub-chassis.
U.S. Pat. No. 5,309,323 teaches a removable electrical unit with combined grip and release mechanism. Each of the removable disk drives is mountable into a corresponding device bay in front of the subsystem chassis. Each removable disk drive incorporates a soft stop and release mechanism.
U.S. Pat. No. 5,224,020 teaches a modular electrical apparatus that includes a plurality of customer removable electrical devices such as disk drives. The devices and support units are all blind pluggable into a removable central electrical distribution unit.
U.S. Pat. Nos. 5,006,959 and 5,119,497 teach a computer apparatus with modular components that includes segregated functional units like a disk array, various plug-in card packages, power/fan unit, and a motherboard. Another goal for moving towards modular computer components is to improve reliability. One concept in the field of disk drives is known as Redundant Array of Independent Disks (RAID). A number of disk drives are interconnected in an array for redundant storage of data. Failure of one disk drive does not destroy irreplaceable data. An example of the RAID concept is disclosed in U.S. Pat. No. 4,754,397 teaches a housing array for containing a plurality of hardware element modules such as disk drives, a plurality of modularized power supplies, and plural power distribution modules, each being connected to a separate source of primary facility power. Each module is self-aligning and blind-installable within the housing and may be installed and removed without tools, without disturbing the electrical cabling within the cabinet, and automatically by a maintenance robot. Despite the advances in designing modular components and associated hardware for computers, there is still a need for a modular component that easily adapts to conventional size restraints, yet benefits from RAID concepts.
U.S. Pat. No. 6,188,571 teaches an apparatus for a mass storage subsystem, such as a RAID array, that includes a housing which defines first and second cavities with the first cavity housing an array controller such as a RAID controller. The second cavity houses a plurality of substantially conventional IDE drives conforming to the 3.5″ form factor. The array is configured to maximize cooling of the array controller and the drives within the extremely small space defined by the housing.
U.S. Pat. No. 6,363,211 teaches video data and audio data that are inputted respectively from a camera system and a microphone and are compressed and encoded in a video compressor/expander-encoder/decoder and an audio compressor/expander-encoder/decoder respectively, and then are multiplexed in a multiplexer. Subsequently the multiplexed data are supplied to a hard disk drive via an AV interface, a host bus, an interface adaptor and an interface. Information representing the kind of the data is written in a register. The data supplied to the hard disk drive are recorded in a disk, on the basis of such information, by a method conforming to the data. And in a reproduction mode, the data are reproduced, on the basis of such information, by a method conforming to the data.
Modern computers utilize data buses to move data from one area of the computer to another. A modern computer has multiple data buses that interconnect different components of the computer system. Computer buses typically are implemented by a series of copper lines within a printed circuit board generally referred to as “traces.” A computer data bus is essentially a shared highway that interconnects different components of a computer system, including a microprocessor, disk-drive controller, memory, and input/output ports. Buses are characterized by the number of bits of data that they are able to transfer at a single time (e.g., an 8-bit data bus simultaneously transfers 8 bits of data in parallel; a 16-bit data bus simultaneously transfers 16 bits in parallel). The bus is integral to internal data transfer. Modern personal computers have specialized data buses to maximize operational efficiency. High performance data buses within modern personal computers are specialized for interconnecting transaction intensive sub-systems. Generally, buses coupled directly to the main processor transfer data at a higher rate than peripheral buses. High-speed buses require special design considerations to ensure system integrity. Industry standards for bus architectures have been created by organizations within the computer industry. One such architecture that is gaining popularity is an architecture containing a “PCI bus.” The PCI bus specification was derived from provisions introduced by Intel Corporation. The Intel provisions detail a local bus system for a personal computer. A PCI compliant circuit-cards can operate in a computer built to PCI standards. Computer industry committees continually review PCI-specification. An operational PCI local bus requires a PCI controller card to regulate bus utilization. Typically, the PCI controller card is installed in one of the PCI card receiving sockets. The PCI controller can exchange data with the computer's central processor, simultaneously transferring either 32 bits or 64 bits of data, depending on the implementation. A PCI controller additionally allows intelligent PCI-compliant adaptors to perform tasks concurrently with the CPU utilizing a technique called “bus mastering.” The PCI specification also allows for multiplexing. Microsoft Press Computer Dictionary 295 (2ed. 1994). Another bus standard is an industry standard bus. A PCI bus is a higher level or faster bus than the Industry Standard (ISA) bus. An ISA bus is typically utilized to interconnect a keyboard to the computer system whereas a PCI bus typically interconnects devices requiring faster communication, such as disk drives and communication interfaces. Due to the high data rate on a PCI bus, the physical interconnection of PCI-compliant circuit boards is critical. Transmission line properties such as interference susceptibility, impedance and length are critical to ensure bus communication integrity.
Computers built to PCI specifications can be upgraded or enhanced by adding PCI-compliant circuit cards. A PCI-compliant circuit board is often referred to as a “PCI card” by those skilled in the art. Printed circuit boards that are sold to consumers generally have been subjected to extensive development and testing prior to their sale. The development phase of a printed circuit board can be very expensive. Design and production defects that avoid detection due to inadequate test capabilities can substantially add to the cost of a product. Production delays due to insufficient testing resources further add to the cost of a product. A conventional personal computer contains a “motherboard” which provides internal buses to interconnect a main processor with other sub-systems of the computer. The motherboard is the main circuit board containing the primary components of the computer system. A PCI circuit board undergoing a thorough development procedure must be electrically connected to an operational computer system. Due to the compactness of motherboards and rigid PCI bus specifications, PCI connectors are typically located close together on a motherboard. Visual access, as well as physical access to electrical signals during operation of PCI compatible circuit boards may be extremely limited. Access to desired locations on a PCI circuit card during a test that utilizes a motherboard requires that the PCI card be remotely located from the motherboard. Testing typically requires an extension cable or an adaptor cable. For example, extension cables can be plugged into the motherboard and the PCI card, then the PCI card can be placed in a location which provides full access. Alternately, special devices such as extender circuit boards can be plugged into a PCI card-receiving socket to extend a duplicative connector at a location above surrounding PCI cards. An extender card places the board under test above surrounding obstructions and allows access to signals on the PCI card. Often, initial PCI card design concepts are hand-wired by technicians. Typically, hand wired prototype circuit boards are physically much larger than allowed by the PCI specification. Hence, many conceptual designs will not fit in a conventional motherboard environment due to space constraints. A commonly utilized development tool is a PCI extender card having right angle connectors. Extender cards with right angles provide access to signals on the topside of the PCI compatible circuit board, however, access to signals on the underside of the PCI card is again limited. Further, only one right angle extender card per system can be attached to the motherboard. Generally, each party to the development of a PCI card has different requirements. A large quantity of application specific extender cards or test fixtures is built during the development of a product. Often, an application specific test fixture is useless after completion of the development of a specific PCI card. Extender cards and test fixtures add to the cost of product development. Additionally, the added transmission line lengths introduced by adaptor cables and/or extender cards can create phenomena which is not present when the PCI card is plugged directly into a motherboard. More particularly, card extenders or adaptors may degrade the signal quality on the PCI bus. Cables having excessive lengths induce data transfer problems, particularly timing skew and interference. Currently, in the development of PCI compatible circuit boards, the circuit boards must operate in an electrical environment that is different from the electrical environment found in actual field operation. Often, not all of the design problems and difficulties can be determined utilizing extender cards and/or adaptor cables. Additionally, problems manifest in the development of PCI circuit cards that are a result of the test environment. It therefore should be obvious that there is a need for a system and method for allowing access to the surface of a PCI compatible circuit board during operational testing. Further, a need exists for a reusable test fixture that accommodates oversized PCI compatible circuit boards. Additionally, it has become apparent that adequate testing of a PCI compatible card requires a test environment that accurately simulates field- operating conditions.
U.S. Pat. No. 5,822,184 teaches a modular data device assembly for a computer is disclosed that has a housing that is designed to fit into a conventional, industry standard size expansion bay. Individual plug-in data storage devices such as hard disk drives or CD-ROM drives are disposed vertically in a stacked formation within the housing. A motherboard with plug-in connectors to which the drives are connected allows easy replacement of defective data devices, which devices slide in or out. The disk drives and modular data device assemblies may be arrayed in series or in parallel to a controller. By its modular structure and redundant storage functions, the present invention benefits from what is known as Redundant Array of Independent Disks principle.
U.S. Pat. No. 6,446,148 teaches a protocol for expanding control elements of an ATA-based disk channel that supports device command and data information issued over the channel to a number of peripheral devices coupled to the channel. In addition, channel command circuitry issues channel commands which control channel related functional blocks, each of which performs non-device specific channel related functions. The channel commands are interpreted by the channel and are not directed to peripheral devices coupled thereto. Channel commands include identification indicia that distinguish a channel command from a device command.
U.S. Patent Application 20020087898 teaches an apparatus that facilitates direct access to a Serial-Advanced Technology Attachment (Serial-ATA) device by an autonomous subsystem in the absence of the main operating system.